The present disclosure relates to a solid-state imaging device, a manufacturing method therefor, a solid-state imaging apparatus, and an image capturing apparatus. Specifically, the disclosure relates to a back-illuminated solid-state imaging device, a manufacturing method therefor, and a solid-state imaging apparatus and an image capturing apparatus using the solid-state imaging device.
In the past, in video cameras, digital still cameras, and the like, solid-state imaging apparatuses constituted by a CCD (Charge Coupled Device) or CMOS image sensor have come into widespread use. In recent years, in accordance with reductions in size and power consumption of video cameras, digital still cameras, and mobile phones equipped with cameras, CMOS solid-state imaging apparatuses have spread rapidly. In addition, in the CMOS solid-state imaging apparatuses, the front-illuminated type shown in FIG. 18 and the back-illuminated type shown in FIG. 19 have been known.
As shown in the schematic configuration diagram of FIG. 18, a front-illuminated solid-state imaging apparatus 111 includes a pixel region 113. In the region, a plurality of photodiodes PD, which constitutes a photoelectric conversion portion of a semiconductor substrate 112, is formed and a plurality of unit pixels 116, which is formed of a plurality of pixel transistors, is formed. Although the pixel transistors are not shown in the drawing, FIG. 18 shows gate electrodes 114, and thus schematically shows the presence of the pixel transistors.
Each photodiode PD is isolated by an element isolation region 115 formed of an impurity-diffused layer. In addition, a multilevel wiring layer 119, in which a plurality of wires 118 is disposed with an interlayer insulation film 117 interposed therebetween, is formed on the surface side of a semiconductor substrate 112 where the pixel transistors are formed. The wires 118 are formed in portions other than portions corresponding to the positions of the photodiodes PD.
On the multilevel wiring layer 119, an on-chip color filter 121 and an on-chip micro lens 122 are formed in this order with a planarization film 120 interposed therebetween. The on-chip color filter 121 is constituted by arranging each color filter of, for example, red (R), green (G), and blue (B).
In the front-illuminated solid-state imaging apparatus 111, the light L is incident from the side of the substrate surface, on which the multilevel wiring layer 119 is formed, as a light receiving surface 123.
On the other hand, as shown in the schematic configuration diagram of FIG. 19, a back-illuminated type solid-state imaging apparatus 131 includes the pixel region 113. In the region, a plurality of photodiodes PD, which constitutes a photoelectric conversion portion of a semiconductor substrate 112, is formed and a plurality of unit pixels 116, which is formed of a plurality of pixel transistors, is formed. Although the pixel transistors are not shown in the drawing, FIG. 19 shows gate electrodes 114, and thus schematically shows the presence of the pixel transistors.
Each photodiode PD is isolated by an element isolation region 115 formed of an impurity diffused layer. In addition, a multilevel wiring layer 119, in which a plurality of wires 118 is disposed with an interlayer insulation film 117 interposed therebetween, is formed on the surface side of a semiconductor substrate 112 where the pixel transistors are formed. In the back-illuminated type, the wires 118 can be formed regardless of the positions of the photodiodes PD.
Further, an insulation layer 128, the on-chip color filter 121, and the on-chip micro lens 122 are formed in this order on the backside of the semiconductor substrate 112 to which the photodiode PD faces.
In the back-illuminated solid-state imaging apparatus 131, the light L is incident from the backside of the substrate, which is the side opposite to the substrate surface on which the multilevel wiring layer 119 and the pixel transistor are formed, as a light receiving surface 132.
Incidentally, there is a demand for high integration of devices achieved by miniaturizing pixels. The above-mentioned front-illuminated solid-state imaging apparatus 111 has a structure in which the photodiodes PD receive light through spaces of the multilevel wiring layer 119. Hence, in accordance with miniaturization of pixels achieved by high integration, it becomes difficult to sufficiently secure the area of the light sensing portion because of obstacles such as wires. Accordingly, there are concerns about deterioration in sensitivity and an increase in shading.
In contrast, in the back-illuminated solid-state imaging apparatus 131, the light L is incident on the photodiodes PD without restriction of the multilevel wiring layer 119. Therefore, the opening of each photodiode PD can be set to be large, and thus high sensitivity is achieved.
However, in the back-illuminated solid-state imaging apparatus 131, it is necessary for the signal processing circuit, which is formed on the side opposite to the light receiving surface side, to read and process signal charges. For this reason, it is necessary to decrease the thickness of the semiconductor substrate 112. Hence, when long-wavelength light such as infrared rays is incident, the light, which is easily transmitted to the multilevel wiring layer 119 and is reflected by the multilevel wiring layer 119, is incident to the photodiodes PD of adjacent pixels, and thus this is likely to mix the colors of the light.
Hence, Japanese Unexamined Patent Application Publication No. 2009-259934 as shown in FIG. 20 proposes the technique of partially providing the infrared cut filter layer 150 between the photodiodes and the wiring layer. Due to the technique disclosed in Japanese Unexamined Patent Application Publication No. 2009-259934, it is possible to cut the infrared rays which are transmitted through the semiconductor substrate 112 and are reflected by the multilevel wiring layer 119, and it is also possible to prevent colors from mixing.